IEEE standard 754 floating point number multiplication using 8bit register

Abstract

Floating point is very important in real applications likes automotive power train and body control applications, imaging such as scaling, transforms and font generation in printing, 3D transforms, FFT and filtering in graphics image and Digital signal processing. This paper presents floating point multiplication and division of IEEE754 format. The floating point multiplication and division which improves the performance of the processor speed and area. This paper designed for floating-point multiplication, emphasizing the utilization of 8-bit registers and effective overflow handling strategies. The module operates within the context of digital systems, processing two 32-bit floating-point numbers represented by four 8-bit inputs each, and generating a 32-bit result through four 8-bit outputs. Key aspects of the module include the extraction of sign, exponent, and mantissa components from the input numbers, which are crucial for performing accurate multiplication. By leveraging 8-bit registers for internal computation, the module optimizes resource utilization while maintaining precision. A significant focus of the module design lies in the detection and management of overflow conditions, which occur when the result exceeds the representable range of the floating-point format. Through careful monitoring of the exponent and significant bits of the mantissa, the module efficiently identifies overflow scenarios and employs appropriate strategies to handle them. In cases of overflow, the module employs techniques such as setting the result to its maximum representable value or zero, ensuring the integrity of the computation within the constraints of the 8-bit register architecture. This paper provides a detailed exploration of the design principles, implementation strategies, and overflow handling mechanisms employed in the Verilog module. Through experimental validation and analysis, the module demonstrates its effectiveness in achieving reliable and accurate floating-point multiplication while leveraging 8-bit registers and addressing overflow challenges.